[2074]
5. Express the complement of the following function in sum of min-terms.
F(A, B, C, D) = Σ(0, 2, 6, 11, 13, 14).
[5]
6. Reduce the following function using k-map
F = wxy + yz + xy'z + x'y .
[5]
[2075]
5. Express the Boolean Function F = A + B'C in a sum of min terms.
[5]
6. Reduce the following function using k-map
F = B'D + A'BC' + AB'C + ABC'.
[5]
[2077]
6. Simplify the following function and implement them with two level NOR gate circuit,
F(w, x, y, z) = wx’ + y’z’ + w’yz’.
[5]
[2078]
7. Express the Boolean function F = x + yz as product of max-terms.
[5]
8. Minimize the Boolean function Boolean function using K-map
F(A, B, C, D) = Σ(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
[5]
[2074]
7. Design a combinational circuit with three inputs and six outputs. The output binary number
should be the square of the input binary number.[5]
10. Design 4-bit even parity generator.[5]
[2075]
7. Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C.
When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the
binary input is 4, 5, 6, or 7, the binary output is one less than the input.[5]
[2077]
1. Design a combinational circuit that generates 9’s complement of a BCD number.
[10]
6. Simplify the following function and implement them with two level NOR gate circuit, F(w, x, y,
z) = wx’ + y’z’ + w’yz’. [5]
8. Design 4-bit even parity generator. [5]
[2078]
6. Derive the Boolean expression for sum and carry of half adder. Draw its combinational circuit.
Implement it using only NAND gates.
[5]
10. Design a combinational circuit with three inputs and one output. The output is 1 when the
binary value of the inputs is an odd number.[5]
[2074]
1. Implement the following function F = Σ(0,3,5,6,7) using
[10]
- Decoder.
- Multiplexer.
- PLA.
2. Differentiate between PLA and PAL.[10]
(half question combined in 10 marks)
3. Draw a block diagram, truth table and logic circuit of 1*16 Demultiplexer and explain its
working principle.[10]
8. Design a 5 x 32 decoder with four 3 x 8 decoder with enable and one 2 x 4 decoder. Use block
diagrams only.[5]
9. Design and explain the Decimal adder with truth table and suitable diagram.[5]
[2075]
1. Implement the following function F = Σ(1, 2, 3, 4, 8) using
[10]
- Decoder.
- Multiplexer.
- PLA.
3.The following is a truth table of a 3-input,4 output combinational circuit. Tabulate the PAL
programming table for the circuit and mark for the circuit and mark the fuses to be blown in a
PAL diagram.
[10]
8. Implement half adder using 2-4 decoder.[5]
10. Design 4-bit even parity generator.[5]
[2077]
2. Implement the following functions using PLA
[10]
- w (A, B, C, D) = Σ(2, 12, 13)
- x (A, B, C, D) = Σ(7, 8, 9, 10, 11, 12, 13, 14, 15)
- y (A, B, C, D) = Σ(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15)
- z (A, B, C, D) = Σ(1, 2, 8, 12, 13)
[2078]
2. Implement the following function F = Σ(0, 2, 3, 4, 7) using
[10]
- Multiplexer.
- Decoder.
- PLA.
11. Differentiate between PLA and PAL. Explain 4-bit magnitude comparator.[5]